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GENLINX TM GS9002A
Serial Digital Encoder
DATA SHEET
FEATURES * fully compatible with SMPTE-259M serial digital standard * supports up to four serial bit rates to 400 Mb/s * accepts 8 bit and 10 bit TTL and CMOS compatible parallel data inputs * X + X + 1 scrambler, NRZI converter and sync detector may be disabled for transparent data transmission * pseudo-ECL serial data and clock outputs * single +5 or -5 volt supply * 713 mW typical power dissipation (including ECL pull-down loads). * 44 pin PLCC packaging * Pb-free and Green APPLICATIONS * 4SC, 4:2:2 and 360 Mb/s serial digital interfaces for Video cameras, VTRs, Signal generators ORDERING INFORMATION
9 4
NOT RECOMMENDED FOR NEW DESIGNS
DEVICE DESCRIPTION The GS9002A is a monolithic bipolar integrated circuit designed to serialize SMPTE 125M and SMPTE 244M bit parallel digital signals as well as other 8 or 10 bit parallel formats. This device performs the functions of sync detection, 9 parallel to serial conversion, data scrambling (using the X + 4 X +1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. It supports any of four selectable serial data rates from 100 Mb/s to over 360 Mb/s. The data rates are set by resistors and are selected by an on-board 2:4 decoder having two TTL level input address lines. Other features such as a sync detector output, a sync detector disable input, and a lock detect output are also provided. The 9 4 X + X + 1 scrambler and NRZ to NRZI converter may be bypassed to allow the output of the parallel to serial converter to be directly routed to the output drivers. The GS9002A provides pseudo-ECL outputs for the serial data and serial clock as well as a single-ended pseudo-ECL output of the regenerated parallel clock. The GS9002A directly interfaces with cable drivers GS9007A, GS9008A and GS9009A. The device requires a single +5 volt or -5 volt supply and typically consumes 713 mW of power while driving 100 loads. The 44 pin PLCC packaging assures a small footprint for the complete encoder function.
Part Number
GS9002ACPM GS9002ACPME3
Package
44 Pin PLCC 44 Pin PLCC
Temperature Pb-Free and Green
oC to 70C oC to 70C No Yes
SCRAMBLER/ SERIALIZER SELECT SYNC DETECT DISABLE PARALLEL DATA IN (10 BITS)
26 6
2:1 MUX
3 38
SYNC DETECT SERIAL DATA SERIAL DATA
7-16 INPUT LATCH
SYNC DETECT
39 P/S CONVERTER SCRAMBLER NRZ NRZI 42
SERIAL CLOCK SERIAL CLOCK
PLD
SCLK
43
LOCK DETECT PCLK IN 17
PHASE FREQUENCY DETECT
20
LOCK DETECT REGULATOR CAP
CHARGE PUMP
VCO
29
LOOP FILTER PCLK OUT
22 19 DIV BY 10 GENERATOR DATA RATE SWITCH
36 35
DRS0 DRS1
34 33 32
RVC00 RVC01 RVC02 RVC03
GS9002A
Patent No.5,357,220
31
FUNCTIONAL BLOCK DIAGRAM
Revision Date: June 2004 Document No. 24149 - 1
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan: Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan Tel: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505
GS9002A - ENCODER DC ELECTRICAL CHARACTERISTICS
NOT RECOMMENDED FOR NEW DESIGNS
VCC = 5V, V EE = 0V, TA = 0C to 70C unless otherwise shown
PARAMETER Supply Voltage Power Consumption
SYMBOL VS PD
CONDITIONS Operating Range
SDO/SDO connected to (V CC -2V) thru 100y resistors, PCK OUT connected to V EE via 1k Same as above with SCK/SCK also connected to (V CC-2V) thru 100 resistors.
MIN 4.75 -
TYP 5.0 690 710
MAX 5.25 870 900
UNITS V mW mW
NOTES
Supply Current
IS
SDO/SDO connected to (VCC-2V) thru 100y resistors, PCK OUT connected to VEE via 1k Same as above with SCK/SCK to (VCC-2V) V thru 100 resistors.
-
155
190
mA
2.0 -
170 2.5 -
205 0.8 10 0.5 4.0 -0.7 -1.5
mA V V A V V mA V V
see Figure 15
TTL Inputs-HIGH TTL Inputs-LOW Logic Input Current TTL Outputs-HIGH TTL Outputs-LOW Sync Detect O/P Serial Outputs (SDO & SCK) High Low
VIHmin VILmax IINmax VOHmin VOLmax IOSYNC VOH VOL
TA = 25C TA = 25C
TA = 25C TA = 25C
2.4 -
SINK & SOURCE with respect to V
CC
TA=25C, RL=100 to VCC-2V (VCC-2V)
-0.875 -1.8
GS9002A - ENCODER AC ELECTRICAL CHARACTERISTICS
VCC = 5V, V EE = 0V, T A = 0C to 70C, V LOOP FILTER =2.6 V unless otherwise shown,
PARAMETER Serial Data Outputs (SDO and SDO) bit rates signal swing rise/fall times jitter Serial Clock Outputs (SCK and SCK) frequency signal swing
SYMBOL BRSDO VSDO tR, tF t J(SDO) SCK VSCK tD tLOCK frequency signal swing rise/fall times jitter PCKO VPCKO tR, tF t JPCKO tR tSU tHOLD
CONDITIONS RL = 100 to (VCC-2 volts) TA = 25C 143 Mb/s 270 Mb/s RL = 100 to (VCC-2 volts) See Figure 9 CLOOP FILT = 0.1F RLOOP FILT = 3.9k RL = 1k to VEE
MIN 100 700 100 10 -
TYP 850 500 400 300 800 1.4 1 800 700 400 -
MAX 400 1000 400 1.2 40 -
UNITS Mb/s mV p-p ps ps p-p ps p-p MHz mV p-p ns ms MHz mV p-p ps ps p-p ps ns ns
NOTES
20% - 80% see Note 1 see Fig. 16 see Fig. 12, 13 see Fig. 14 Data lags Clock
Serial Data to Clock Timing Lock Time Parallel Clock Output (PCK OUT)
PCKO = SCK/10
20% - 80%
Parallel Data & Clock Inputs risetime setup hold
TA = 25C
500 3 3
NOTE 1: Measured using PCK-IN as trigger source on 1GHz analog oscilloscope.
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ABSOLUTE MAXIMUM RATINGS
NOT RECOMMENDED FOR NEW DESIGNS
PARAMETER Supply Voltage Input Voltage Range (any input) DC Input Current (any one input) Power Dissipation (VS = 5.25 V) Operating Temperature Range Storage Temperature Range Lead Temperature (soldering 10 seconds)
VALUE/UNITS 5.5 V -VEE < VI < VCC 10 mA 1W 0C TA 70C -65C TS 150C 260C
SYNC DET. DIS. VCC1
VEE
SYNC DET. VCC3
VEE
VEE
SCK
SCK
VCC2a
VCC2b
6 PD0 7
5
4
3
2
44
43
42
41
40 39 SDO
PD1 PD2 PD3 PD4
8
38
SDO
9
37
VEE DRS0
PARALLEL DATA INPUTS
10
36
11
35
DRS1
PD5
12
GS9002A TOP VIEW
34
RVC00 VCO FREQUENCY SET RESISTORS
PD6
13
33
RVC01 RVC02
PD7 PD8
14
32
15
31
RVC03
PD9
16
30
VEE C. REG
PCK IN
17 18 19 20 21 22 23 24 25 26 27 28
29
VEE
PCK OUT
LOCK DET.
VCC3 LOOP FILT.
VEE
NC
VEE
SSS
VEE
VCC3
Fig. 1 GS9002A Encoder Pin Connections
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GS9002A Serial Digital Encoder - Detailed Device Description
NOT RECOMMENDED FOR NEW DESIGNS
The GS9002A Encoder is a bipolar integrated circuit used to convert parallel data into a serial format according to the SMPTE 259M standard. The device encodes both eight and ten bit TTL-compatible parallel signals producing serial data rates up to 400 Mb/s. It operates from a single five volt supply and is packaged in a 44 pin PLCC. Functional blocks within the device include the input latches, sync detector, parallel to serial converter, scrambler, NRZ to NRZI converter, ECL output buffers for data and clock, PLL for 10x parallel clock multiplication and lock detect. The parallel data (PD0-PD9) and parallel clock (PCK-IN) are applied via pins 7 through 17 respectively. Sync Detector The Sync Detector looks for the reserved words 000-003 and 3FC-3FF, in ten bit Hex, or 00 and FF in eight bit Hex, used in the TRS-ID sync word. When the occurrence of either all zeros or ones at inputs PD2-PD9 is detected, the lower two bits PD0 and PD1 are forced to zeros or ones, respectively. This makes the system compatible with eight or ten bit data. For non SMPTE standard parallel data, a logic input, Sync Disable (6) is available to disable this feature. Scrambler The Scrambler is a linear feedback shift register used to pseudo-randomize the incoming serial data according to the fixed polynomial (X9+X4+1). This minimizes the DC component in the output serial data stream. The NRZ to NRZI converter uses another polynomial (X+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. Phase Locked Loop The PLL performs parallel clock multiplication and provides the timing signal for the serializer. It is composed of a phase/frequency detector, charge pump, VCO and a divide-by-ten counter. The phase/frequency detector allows a wider capture range and faster lock time than that which can be achieved with a phase discriminator alone. The discrimination of frequency also eliminates harmonic locking. With this type of discriminator, the PLL can be over-damped for good stability without sacrificing lock time. The charge pump delivers a 'charge packet' to the loop filter which is proportional to the system phase error. Internal voltage clamps are used to constrain the loop filter voltage between approximately 1.8 and 3.4 volts. The VCO, constructed from a current-controlled multivibrator, features operation in excess of 400 Mb/s and a wide pull range (40% of centre frequency).
VCO Centre Frequency Selection The wide VCO pull range allows the PLL to compensate for variations in device processing, temperature variations and changes in power supply voltage, without external adjustment. A single external resistor is used to set the VCO current for each of four centre frequencies as selected by a two bit code through a 2:4 decoder. The current setting resistors are connected to the RVCO0 through RVCO3 inputs (34, 33, 32 and 31). The decoder inputs DRS0 and DRS1 (36, 35) are TTL compatible inputs and select the four resistors according to the following truth table.
DRS1 0 0 1 1
DRS0 0 1 0 1
Resistor Selected RVCO0 (34) RVCO1 (33) RVCO2 (32) RVCO3 (31)
A 2:1 multiplexer (MUX) selects either the direct data from the P/S Converter (Serializer) or the NRZI data from the Scrambler. This MUX is controlled by the Scrambler/Serializer Select (SSS) input pin 26. When this input is LOW the MUX selects the Scrambler output. (This is the mode used for SMPTE 259M data). When this input is HIGH the MUX directly routes the serialized data to the output buffer with no scrambling or NRZ to NRZI conversion. The lock detect circuit disables the serial data output when the loop is not locked by turning off the 2:1 MUX. The Lock Detect output is available from pin 20 and is HIGH when the loop is locked. The true and complement serial data, SDO and SDO are available from pins 38 and 39 while the true and complement serial clock, SCK and SCK are available from pins 43 and 42 respectively. If the serial clock is not used pins 43 and 42 can be connected to VCC. The regenerated parallel clock (PCK OUT) is available at pin 19. This output is a single ended pseudo-ECL output requiring a pull down resistor. If regenerated parallel clock is not used pin 19 can be connected to VCC.
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GS9002A PIN DESCRIPTIONS
NOT RECOMMENDED FOR NEW DESIGNS
PIN NO. 1 2 3
SYMBOL VEE VCC3 SYNC DET.
TYPE
DESCRIPTION Power Supply: Most negative power supply connection. Power Supply: Most positive power supply connection for the PLL and scrambler.
O
TTL output level that detects the occurrence of all zero's or all one's at inputs PD2-PD9 and pulses LOW for three PCK-IN durations. Used to detect SMPTE 259M reserved words (000-003 and 3FC-3FF) in TRS sync word. Parallel data bits PD0 and PD1 are set Low or High when PD2 - PD9 are Low or High respectively. Power Supply: Most negative power supply connection. Power Supply: Most positive power supply connection for the input data latches and serializer.
4 5 6 7-16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
VEE VCC1 SYNC DET. DISABLE PD0-PD9 PCK-IN VEE PCK OUT LOCK DET. VCC3 LOOP FILT. VEE NC VEE SSS VEE VCC3 CREG VEE RVCO3 I I I I O O I I I
TTL level input that disables the internal Sync Detector when HIGH. This allows the GS9002 to serialize 8 or 10 bit non - SMPTE Standard parallel data. TTL level inputs of the parallel data words. PD0 is the LSB and PD9 is the MSB. TTL level input of the Parallel Clock. Power Supply: Most negative power supply connection. Pseudo-ECL output representing the re-clocked Parallel Clock and is derived from the internal VCO. The VCO is divided by 10 in order to produce this output. TTL level output which goes HIGH when the internal PLL is locked. Power Supply: Most positive power supply connection for the PLL and scrambler. Connection for the R-C loop filter components. The loop filter sets the PLL loop parameters. Power Supply: Most negative power supply connection.
Power Supply: Most negative power supply connection. Scrambler/Serializer Select. TTL level input that selects scrambled NZRI output when logic LOW or direct serializer output when logic HIGH. Power Supply: Most negative power supply connection. Power Supply: Most positive power supply connection for the PLL and scrambler. Compensation RC network for internal voltage regulator that requires decoupling with a series 0.1F capacitor and 820 resistor. Components should be located as close as possible to the pin. Power Supply: Most negative power supply connection. VCO Resistor 3: Analog current input used to set the centre frequency of the VCO when the two Data Rate Select bits (pins 35 and 36) are both set to logic 1. A resistor is connected from this pin to VEE. VCO Resistor 2: Analog current input used to set the centre frequency of the VCO when the Data Rate Select Bit 0 (pin 36) is set to logic 0 and the Data Rate Select Bit 1 (pin 35) is set to logic 1. A resistor is connected from this pin to VEE. VCO Resistor 1: Analog current input used to set the centre frequency of the VCO when the Data Rate Select Bit 0 (pin 36) is set to logic 1 and the Data Rate Select Bit 1 (pin 35) is set to logic 0. A resistor is connected from this pin to VEE. VCO Resistor 0: Analog current input used to set the centre frequency of the VCO when the two Data Rate Select bits (pins 35 and 36) are both set to logic 0. A resistor is connected from this pin to VEE. TTL level inputs to the internal 2:4 demultiplexer used to select one of four VCO frequency setting resistors (RVCO0 - RVCO3). (See above)
32
RVCO2
I
33
RVCO1
I
34
RVCO0
I
35,36
DRS0, 1
I
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GS9002A PIN DESCRIPTIONS (Continued)
NOT RECOMMENDED FOR NEW DESIGNS
PIN NO 37 38,39
SYMBOL VEE SDO/SDO
TYPE
DESCRIPTION Power Supply: Most negative power supply connection.
O
Serial Data Outputs (true and inverse). Pseudo-ECL differential outputs representing the serialized data. These outputs require 390 pull down resistors. Power Supply: Most positive power supply connection for the Serial Data ECL output buffers. Power Supply: Most positive power supply connection for the Serial Clock ECL output buffers.
40 41 42,43
VCC2b VCC2a SCK/SCK O
Serial Clock Outputs (inverse and true). Pseudo-ECL differential outputs of the Serial Clock (10x Parallel Clock). These outputs require 390 pull-down resistors.
44
VEE
Power Supply: Most negative power supply connection.
INPUT / OUTPUT CIRCUITS
VCC 5k
VCC
1k
1k
INPUT
SYNC DET
VR1
VEE
VEE
Fig. 2 Pin No. 3 Sync Detect
Fig. 3 Pins No. 6, 7 - 16, 17,26 Sync Disable, Parallel Data, Parallel Clock, Scrambler/Serializer Select
VCC VCC
VCC
1k
1k
10k
PCK OUT
LOCK DETECT
VEE
VEE
Fig. 4 Pin No. 19 Parallel Clock Out
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Fig. 5 Pin No. 20 Lock Detect
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VCC
VCC
IVCO
NOT RECOMMENDED FOR NEW DESIGNS
VSELECT
VR2=2.15V
DRS0
DRS1
800
RVCOX
VR1
VEE
VEE
Fig. 7 Pins No. 31 - 34 Frequency Setting Registors RVCO0-RVCO3 Fig. 6 Pins No. 35, 36 Data Rate Select
VCC
200
200
SDO
SDO
VEE
Fig. 8 Pins No. 38, 39, 42, 43 Serial Outputs (Data & Clock)
tCLKL = tCLKH tD tD
PARALLEL CLOCK PLCK
50%
SERIAL DATA OUT (SD0)
PARALLEL DATA PDn
SERIAL CLOCK OUT (SCK)
50%
50%
tSU
tHOLD
Fig. 9 Waveforms
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4sc DATA STREAM
T R S
ACTIVE VIDEO & H BLANKING
T R S
ACTIVE VIDEO & H BLANKING
T R S
NOT RECOMMENDED FOR NEW DESIGNS
SYNC DETECT
4:2:2 DATA STREAM
E A V
H BLNK
S A V
ACTIVE VIDEO
E A V
H BLNK
S A V
SYNC DETECT
PCLK IN
PDN
XXX 3FF
000
000
XXX
***
***
XXX
3FF
000
000
XXX
***
SYNC DETECT
Fig. 10 Timing Diagram
+5V
LOOP LOCKED L.E.D.
330
+10 2N4400 0.1 10k 82
5k
6x100n
+5V
20
26 SSS
6
2,5,21,28,40,41 100 38 SDO 39 SDO 43 SCK 100 100 100 DATA DATA
DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 DATA 7 DATA 8 DATA 9 CLOCK *150 *10p
7 8 9
PD0 PDI PD2
LOCK DET.
SYNC (6x VCC) DIS.
10 PD3 11 PD4 12 PD5 13 PD6 14 PD7 15 PD8 16 PD9
17 PCK IN 36 DRS0
CLOCK CLOCK +5V 1M
GS9002A
SCK 42
19 PCK-OUT PARALLEL CLOCK OUT 0.1
10k
10k
35 DRS1 22 LOOP FILT 29 CREG RVCO1 RVCO2 RVCO3 RVCO4 VEE 34 33 32 31 1,4 18,23 0.1 25,27 30,37 1 2 34 44 820 4x0.1
3.9k
1k COMMON
DATA RATE SELECT DIP SWITCH (SEE TRUTH TABLE, FIG. 2)
+5V
NOTES: Resistors 1, 2, 3 and 4 are used to set the VCO centre frequency. For 143/177 Mb/s 6k, 270 Mb/s 2.7k, 360 Mb/s 1.8k All resistors in ohms, all capacitors in microfarads unless otherwise stated. represent test points.
* This RC network is used to slow down fast PCLK risetimes ( 500ps).
It is not required if risetimes exceed 500ps.
Fig. 11 GS9002A Test Circuit
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TYPICAL PERFORMANCE CURVES (VS = 5V, TA = 25 C unless otherwise shown)
NOT RECOMMENDED FOR NEW DESIGNS
600 550 500
600 550 500
VCO FREQUENCY (MHz)
FREQUENCY (MHz)
450 400 350 300 250 200 150 100 50 0 1 2 3 4 5 6 7 8 9 10
450 400 350 300 250 200 150 100 50 0 1.8 2.0
OPTIMAL LOOP FILTER VOLTAGE
RVCO = 1.8k
V
LOOP
=2.6V
RVCO = 2.7k
RVCO = 6.3k
2.2
2.4
2.6
2.8
3.0
3.2
3.4
FREQUENCY SETTING RESISTANCE (ky)
LOOP FILTER VOLTAGE (V)
Fig. 12 VCO Frequency
Fig. 13 VCO Frequency vs Loop Filter Voltage
1000
200
V = 5.25V
950
S
V = 5.25V
S
190
SERIAL OUTPUT (mV)
900
CURRENT (mA)
V = 5.0V
S
850
180
V = 5.0V
S
800
170
V = 4.75V
S
V = 4.75V
S
750
160
700 0 10 20 30 40 50 60 70 150 0 10 20 30 40 50 60 70
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
Fig. 14 Serial Output Level (Data & Clock)
Fig. 15 Supply Current
800 700 600
JITTER p-p (ps)
500
143 Mb/s
400
270 Mb/s
300 200 100 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
LOOP FILTER VOLTAGE (V)
Fig. 16 Output Jitter
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NOT RECOMMENDED FOR NEW DESIGNS
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+5V 10 + 10 0.1 6x100n 8 20 26 6 2,5,21,28,40,41 OUT 1 OUT 1 OUT 2 3 OUT 2 4 2 1 1.0 1.0 1.0 68 68 1p8 2N4400 +
LOOP LOCKED L.E.D.
10k
SDO1 (75)
330
5k
+5V
SDO1 (75)
VCC
1p8
DATA 0 PD0 PDI SDO 39 SDO 390 390 6 100 38 100 7
*100
7 8
SER. IN SER . IN LOCK DET. SSS SYNC (6x VCC) DIS.
DATA 1
100
DATA 2 PD2
100
9
CABLE DRIVER GS9007A
DATA 3
100
DATA 4
100
DATA 5
100
68 1.0 4x150 68 1p8
1p8
DATA 6 +5V SCK SCK 19 PCK-OUT 22 47 27 100 47 0.1 LOOP FILT 42 1M 43 5
100
GS9002A
VEE
100
DATA 7
100
DATA 8
10 PD3 11 PD4 12 PD5 13 PD6 14 PD7 15 PD8 16 PD9 17 PCK IN
36 DRS0 35 DRS1 29
SDO2 (75)
DATA 9
100
CLOCK
100
PARALLEL CLOCK T.P.
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CREG RVCO0 RVCO1 RVCO2 RVCO3 VEE 34 33 32 31 1,4 0.1 18,23 0.1
10pF
SDO2 (75)
1k
10k
10k
820
1 3.9k 180 2 3 4 4x0.1
25,27 30,37 44 0.1
DRS1
18p
DRS0 0 0 1 1 0 1 0 1
RVCO NO. 0 1 2 3
DATA RATE SELECT TRUTH TABLE This signal is 12dB below actual SCK level and is used for test purposes
SERIAL CLOCK (50)
DATA RATE SELECT DIP SWITCH (SEE TRUTH TABLE)
+5V
NOTES: Resistors 1, 2, 3 and 4 are used to set the VCO centre frequency. See Figures 12 and 13. All resistors in ohms, all capacitors in microfarads unless otherwise stated. represent test points. * These resistors are used to slow down fast INPUT edges ( 500ps ) and prevent the input signals from ringing below the VEE rail.
Fig. 17 GENLINX TM Serial Digital Chipset GS9002/7A Application Circuit
APPLICATION CIRCUIT
NOT RECOMMENDED FOR NEW DESIGNS
Figure 17 shows a typical application circuit of the GS9002A driving a GS9007A cable driver.
DOCUMENT IDENTIFICATION
PRODUCT PROPOSAL This data has been compiled for market investigation purposes only, and does not constitute an offer for sale.
REVISION NOTES Added lead-free and green information.
For latest product information, visit www.gennum.com
ADVANCE INFORMATION NOTE This product is in development phase and specifications are subject to change without notice. Gennum reserves the right to remove the product at any time. Listing the product does not constitute an offer for sale. PRELIMINARY The product is in a preproduction phase and specifications are subject to change without notice. DATA SHEET The product is in production. Gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright March 1991 Gennum Corporation. All rights reserved. Printed in Canada.
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